gEDA Project
The gEDA project has produced and continues working on a full GPL'd suite and toolkit of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production.
System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware...
RivieraPRO addresses verification needs of engineers crafting tomorrow’s cuttingedge FPGA and SoC devices. RivieraPRO enables the ultimate testbench productivity, reusability, and automation by combining the highperformance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
fpga asic vhdl verilog system-verilog systemc