gEDA Project
The gEDA project has produced and continues working on a full GPL'd suite and toolkit of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production.
System Verilog, Verilog, VHDL, SystemC HDL Simulator for ASIC Design and Verification.
System Verilog, Verilog, VHDL, SystemC HDL Simulator for ASIC Design and Verification
fpga asic vhdl verilog system-verilog
The gEDA project has produced and continues working on a full GPL'd suite and toolkit of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production.
Free Open Source Linux
System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware...
Commercial Windows
HDL Simulator of System Verilog, Verilog, and VHDL for ASIC design and verification.
Commercial Windows Linux